Automatic gain control circuit and an rf receiver and method using such a circuit

ABSTRACT

An automatic gain control (AGC) circuit including: a forward transmission path ( 214 ) having applied at its input an input RF signal and to provide at its output an output signal; a variable gain AGC amplifier ( 210 ) in the forward transmission path for processing the input RF signal, which amplifier has a control input  240  and is responsive to a control signal applied at its control input to vary its gain; a feedback loop ( 220  to  240 ), coupled from the output of the forward transmission path and to the control input of the AGC amplifier; an integrator ( 230, 232 ), coupled to the control input of the amplifier; a voltage source ( 234 ), coupled to the integrator and to the control input of the amplifiers; and a further variable gain device ( 215 ) for varying the gain or attenuation of a signal applied to the control input of the AGC amplifier.

FIELD OF THE INVENTION

The present invention relates to an automatic gain control circuit andan RF receiver and a method using such a circuit.

BACKGROUND OF THE INVENTION

A radio communication system includes, as a minimum, a transmitter and areceiver. The transmitter and the receiver (which are often each part ofcombined transceiver unit) are interconnected by a radio-frequency (RF)wireless channel, which provides transmission of a communication signalbetween them. A receiver generally includes an amplifier, which iscoupled to a receiving element (an antenna). The amplifier has a gain,which can be adjusted in a predetermined range, using a control signal.Many receivers also include a device which automatically adjusts thegain of the amplifier according to the level of the received signal. Theprocess of adjusting the gain, according to which a received signalshould be amplified, is called Automatic Gain Control (AGC). AGCcircuits which are required to operate rapidly when they detect a signalare known in the art as fast attack AGC circuits.

In Time Division Multiple Access (TDMA) communication systems, an RFchannel is shared among users attempting to access the radio system incertain of the time-division-multiplexed time slots. This enablestransmission of more than one signal at the same frequency, allowing thesequential time-sharing of each channel by two or more users. The timeslots are arranged in periodically repeating frames. Each of the framesincludes a certain number of time slots and each of the slots provides asignal for a specified user. Nowadays, the signal is in a digital form.

TETRA (Trans-European Trunked Radio (also known as Terrestrial TrunkedRadio)) is a system specified by the European TelecommunicationsStandards Institute (ETSI) in which a set of standards are laid down bywhich digital communications especially in a TDMA form are to take placein modern communications. In particular, TETRA Direct Mode Operation(DMO) (defined in European standard ETS 300-396-2), for example, fordirect communication between users operates using 1:4 TDMA format. Eachframe is divided into four time slots. Each receiver operating in thissystem receives a signal in only one of the four time slots per frame.Such systems require either receivers that have a dynamic range largeenough to account for all signal levels and/or a receivers with a veryfast AGC, which can adapt very rapidly to changing levels of receivedsignals. The received signal has a preamble length of about 0.2 ms andthe AGC response should be established during this period.

In particular, where DMO communications between two transceivers ormobile stations is carried out according to TETRA standard procedures, areceiver should be able to receive a DMO signal within a sensitivitylevel range of from −112 dBm to −20 dBm, i.e. 92 dB of dynamic range. Inpractice, signals can be in the dynamic range of from −112 dBm to 0 dBm.In addition, a DMO transmitter is permitted to have 6 dB overshoot atthe beginning of the signal slot and the DMO receiver is required to beable to cope with this overshoot. This overshoot is additional to anovershoot that is usually caused by the circuit response of an AGCcircuit to a step function at the beginning of a DMO signal slot. Inview of these requirements an AGC circuit is required which givesimproved fast attack performance compared with such circuits known inthe prior art, a typical example of which is described in the followingreference.

U.S. Pat. No. 5,742,899 to Blackburn et al., entitled “Fast AttackAutomatic Gain Control (AGC) Loop for Narrow Band Receiver” is directedto a fast attack AGC loop having a first feedback loop with selectableresponse shapes and a second feedback loop with selectable responseshapes. Response shape selection is based upon fast pull-down operationmode, overshoot recovery operation mode and steady state operation mode.The system described in the this reference is dedicated for operating inTDMA, and its response time is 1.5 ms for 25 kHz intermediate frequencybaseband. The system has been optimized for the case when there iscontinuous transmission of RF power, thus allowing AGC settling to occurat the end of a time slot.

However, the prior art loop described in the said reference is notsuitable for use in narrow band RF receivers or transceivers, e.g. foruse in TDMA, in which the RF power is received in discontinuous bursts,such as in the TETRA Direct Mode Operation (DMO) because the responsetime of the loop is not sufficiently fast.

The Applicant's Copending EP Application No. 01116531.3 filed 9^(th)Jul. 2001 (corresponding to U.S. Ser. No. 09/614668 filed 12^(th) Jul.2000) describes an AGC circuit which provides an improvement over theprior art. The purpose of the present invention is to provide a furtherimproved AGC circuit for use in a radio communications receiver(transceiver).

SUMMARY OF THE PRESENT INVENTION

In accordance with the present invention in a first aspect, there isprovided an automatic gain control (AGC) circuit comprising:

a forward transmission path having, in use, applied at its input aninput RF signal and to provide at its output an output signal;

a variable gain AGC amplifier in the forward transmission path forprocessing the input RF signal, which amplifier has a control input andis responsive to a control signal applied at its control input to tovary its gain;

a feedback loop, coupled from the output of said forward transmissionpath and to said control input of said AGC amplifier, said feedback loopincluding a signal detector that has a predetermined non-linear gainresponse, depending on an input signal level, the gain being higher forgreater input signal strength,

an integrator, coupled to said control input of said amplifier; and,

a voltage source, coupled to said integrator and to said control inputof said amplifier,

the circuit being characterised by the fact that it also includes afurther variable gain device for varying the gain or attenuation of asignal applied as an input signal to the control input of said AGCamplifier.

The further variable gain device may comprise a further variable gainamplifier. The variable gain amplifier may be arranged to vary the gainor attenuation of a signal delivered in the feedback loop as a controlinput signal to the AGC amplifier. The further variable gain amplifiermay for example be arranged to vary the gain of a signal applied as aninput to said signal detector. The further variable gain amplifier maybe included in the forward transmission path after the variable gain AGCamplifier (a forward direction being considered as the direction inwhich an input RF signal is passed for processing). The further variablegain device may have a control input connected to a circuit controldevice, e.g. a microcontroller. The circuit control device may beoperable to generate control signals and apply them at the control inputof the further variable gain device to adjust or change the gain of thefurther variable gain device.

The AGC circuit may in the normal way be operable to adjust the gain ofthe AGC amplifier rapidly in response to detection of an input R.F.signal applied to the AGC amplifier, such a rapid adjustment beingreferred to herein as an ‘attack’. The period until the gain of the AGCsubstantially settles following initial detection of an input RF signalis referred to herein as an ‘attack and settling period’.

The further variable gain device in the circuit according to the firstaspect of the invention may be operable such that the signal applied asan input signal to the control input of the AGC amplifier via thefeedback loop is adjusted in gain during an attack of the AGC circuit.The further variable gain device may be operable to have two or moregain levels during an attack and settling period. The gain of thefurther variable device may in operation be adjusted so that in a firstpart of the attack and settling period from a time T0 when an input RFsignal is first applied to the AGC amplifier until a time T1 the gain ofthe further variable gain device is set at a lower level than in asecond part the attack and settling period after the time T1. Thefurther variable gain device may be operable such that during the firstsaid part of the attack and settling period its gain is between 5 dB and20 dB lower than in the said second part of the attack period. The timeT1 may be a time of at least 50 μsec, desirably between between 100 μsecand 300 μsec, especially between 100 μsec and 200 μsec, after the timeT0 and the higher gain second part of the attack period may start at thetime T1. The difference in gain between the two gain levels of thevariable gain device may correspond to the difference (determined bytheory or experiment) between a peak overshoot level of the receiver(forward transmission path) output signal obtained using the higher gainlevel and a steady state level of the receiver output signal using thehigher level gain. In practice the difference in gain between the twogain levels of the variable gain device may be between 5 dB and 20 dB,e.g. particularly between 9 dB and 15 dB.

In the AGC circuit according to the first aspect of the invention, theforward path may, as in the prior art, include a mixer to which anoutput signal from the AGC amplifier is applied. The mixer may comprisea down mixer providing as an output signal a detected signal at basebandfrequency. The further variable gain device may be arranged to adjustthe gain of an output signal from the mixer.

The forward transmission path may include one or more filters, e.g. lowpass filters, e.g. located in the forward transmission path after amixer. As in known circuits, an amplifier may be contained in theforward path after the or each such filter. The said further variablegain device may comprise one or more of such amplifiers. Where there isa chain of filter amplifier pairs along the forward path, the variablegain amplifier may comprise the last such amplifier in the chain,although it could alternatively be another amplifier in the chain.

The circuit according to the first aspect of the invention may includeat least two feedback loops connected between the forward transmissionpath and the control input of the AGC amplifier, including (i) a firstfeedback loop connected to the forward transmission path before the lowpass filter or, where there are a plurality of filters, before one ofthe filters, e.g. the first filter encountered by an input RF signalafter processing by the AGC amplifier, e.g. between a mixer and thefilter, and (ii) a second feedback loop connected to the forwardtransmission path after the filter or at least one of the filters, e.g.the last filter where there is a plurality of filters in the forwardtransmission path, each of the feedback loops incorporating a signaldetector having a non-linear response gain response.

In the AGC circuit according to the first apsect of the invention anoutput signal provided at the output of the forward transmission pathmay include as phase components an in-phase (I) component and aquadrature (Q) component. The or each said signal detector of thefeedback loop(s) may comprise an AGC detector, which in use receives theoutput signal and provides an output signal to the control input of saidAGC amplifier, the output signal being related to a non-linearcombination of the I and Q phase components of said output signal. Theor each detetor may be a sum of squares (SOS) detector providing anoutput related to the sum of the squares of the level of the I and Qphase components.

In operation of the AGC circuit according to the first aspect of theinvention, dependence of the gain G of the or each said signal detectoron the level S of the baseband signal presented thereto may be arelationship represented by:G=G ₀ +kS ^(1+Δ),  (Equation 1)where G is the gain of AGC loop 200, S is the signal level and G₀, k and▭ are predetermined parameters (G₀, k,

. It is noted, that

can be a function of S.

A response of the or each said signal detector, to changes in the levelof the signal presented thereto, may be to provide a loop of variablebandwidth, wherein the variable bandwidth is higher according to thestrength of the input signal being higher.

A dependence of the variable bandwidth BW on the level S of the inputbaseband signal may be represented by:BW=A·(1+Δ)·S ^(Δ)  (Equation 2)where BW is a loop bandwidth, and A is a predetermined parameter.

An AGC circuit according to the first aspect of the invention whichincludes a first feedback loop and a second feedback loop as describedearlier may be such that the signal detector of the first feedback loophas a signal strength detection threshold which is greater than that ofthe signal detector of the the second feedback loop.

In the AGC circuit according to the first aspect of the invention theintegrator may comprise an integrating capacitor and a resistor, theintegrating capacitor having an output through the resistor coupled tothe control input of the AGC amplifier. The voltage source may provideto the integrator, thereby determining a level of control signal at thecontrol input, a predetermined voltage for a predetermined preset timeperiod beginning at a predetermined time.

The control input to the AGC amplifier may include a driver providing asubstantially linear change in amplifier gain or attenuation at the AGCamplifier in response to the voltage applied thereto.

The AGC circuit according to the first apsect of the invention mayinclude switching means allowing the AGC circuit to be switched betweena first mode of operation in which the or each feedback loop is notoperational and a second mode of operation in which the or each feedbackloop is operational, such modes being obtained at predetermined timesfor predetermined time periods. The switching means may include anelectrically operated switch for connecting an output terminal of thesignal detector to the integrator, electrically controlled switches forconnecting voltage source to the integrator and the integrator to thecontrol input of the variable gain amplifier and a controller forproviding signals to operate the switches to provide switching betweenthe first and second modes. Switching between the modes may in operationbe under the control of a circuit control device which may in practicebe the same device employed to control the gain of the further variablegain device.

According to the present invention in a second aspect there is providedan RF receiver including an AGC circuit according to the first aspect.The RF receiver may be operable to receive RF signals provided in aplurality of signal time slots, each pair of adjacent signal time slotsbeing interleaved by at least one empty time slot. The received signalmay occupy one time slot of each four-slot frame of a communicationsoperations mode, the other three slots received being empty.

In such operations, the AGC circuit may have a first operational mode inwhich the or each feedback loop is not operational and a secondoperational mode in which the or each feedback loop is operational, suchmodes being obtained at predetermined times for predetermined timeintervals corresponding to a pattern of the signal time slots and emptytime slots of the signal to be received. The first mode of operation isdesirably initiated after the end of each signal time slot. The secondmode of operation is desirably initiated before the start of each signaltime slot.

The RF receiver according to the second aspect of the invention may beoperable such that the signal to be detected is a signal received indiscontinuous RF bursts, e.g. as in a direct mode operation (DMO)communications signal, usually from a transmitter operating in the samemode. The receiver and the transmitter may both be transceiversoperating according to a TDMA communication procedure, e.g. for use inmobile communications units. The receiver and the correspondingtransmitter may communicate in accordance with TETRA standardprocedures.

According to the present invention in a third aspect there is provided amethod of detecting an RF signal provided in a plurality of signal timeslots, each pair of adjacent signal time slots being interleaved by atleast one empty time slot, the method including use of a RF receiveraccording to the second aspect of the invention.

The present invention beneficially provides a novel AGC circuit,receiver incorporating the same and a method of operating the receiverto provide a fast attack automatic gain for narrow band systems with aresponse time of 0.5 ms or less, in many cases 0.2 ms or less, makingthe circuit, receiver and method suitable for use in detecting RFsignals provided in discontinuous bursts in a TDMA system, especiallywhen operating in DMO. In particular, the AGC circuit according to theinvention beneficially allows a receiver incorporating it to dealefficiently with the above described wide variation of dynamic range andovershoot permitted in TDMA systems such as TETRA DMO as well asminimising the overshoot caused internally by its own response process.

Embodiments of the present invention will now be described by way ofexample with reference to the accompanying drawings, in which:

BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS

FIG. 1 is a schematic circuit diagram illustrating a fast attackautomatic gain control (AGC) circuit, constructed and operational inaccordance with an embodiment of the present invention;

FIG. 2 is a graphical illustration of relationship between signal leveland AGC detector gain in the AGC circuit of FIG. 1, constructed andoperational in accordance with an embodiment of the present invention;

FIG. 3 is a schematic illustration of a method for operating the AGCcircuit of FIG. 1;

FIG. 4 is a graphical illustration of AGC amplifier gain or attenuationversus time illustrating modes of operation of the circuit of FIG. 1;

FIG. 5 is a graph of receiver output voltage (output of the variablegain amp of the circuit of FIG. 1) versus time for two different gainsof the variable gain amplifier of the circuit of FIG. 1;

FIG. 6 is a graph as shown in FIG. 5 showing additionally a furthercurve for receiver output voltage obtained in practice by switchingbetween two loop gains; and,

FIG. 7 is a schematic circuit diagram illustrating a fast attack AGCcircuit, constructed and operable in accordance with a furtherembodiment of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

Reference is now made to FIG. 1, which is a schematic illustration of afast attack AGC loop, generally referenced 200, constructed and operablein accordance with an embodiment of the present invention.

AGC loop 200 includes an AGC amplifier 210 in a forward transmissionpath 214, a down mixer 212 and a variable gain amplifier 215 also in theforward transmission path 214, a driver 216, an AGC detector 218, acontroller 226, a damping resistor R_(AGC) 230, an integrating capacitorC_(AGC) 232, a voltage source V_(PRESET) 234 and three switches 236, 238and 244. AGC amplifier 210 is coupled to down mixer 212 and to driver216. The down mixer 212 is coupled to the variable gain amplifier 215.The AGC detector 218 is coupled via a connection 220 to the variablegain amplifier and at its output to switch 244. Controller 226 iscoupled to switches 236, 238 and 244 and also to variable gain amplifier215. Driver 216 is coupled to switches 238 and 244. Voltage sourceV_(PRESET) 234 is coupled to switch 236. Damping resistor R_(AGC) 230 iscoupled to integrating capacitor C_(AGC) 232 and to switch 238.

The input to AGC loop 200 is an input RF signal. AGC amplifier 210receives the input R.F. signal, amplifies it and provides it to downmixer 212. The output of down mixer 212 is typically a complex basebandsignal, having phase components, i.e. an in-phase (I) component and aquadrature (Q) component. The output of the down mixer is applied to thevariable gain amplifier 215 the operation of which is described furtherbelow. A sample of the baseband signal provided as an output from thevariable gain amplifier 215 is delivered via connection 220 to AGCdetector 218. An output signal produced by AGC detector 218 is fed tointegrating capacitor 232 which produces a gain control signal 240applied to the AGC amplifier 210 via a driver 216 in order to controlthe gain of the AGC amplifier 210. Driver 216 produces a generallylinear slope response in the AGC amplifier 210, where the slope isdefined as decibels (dB) of attenuation per volt change in AGC gaincontrol signal 240. The response could however be a non-linear one. Thevalue of AGC gain control signal 240 depends on the operation mode ofAGC loop 200. Detailed description of each of the operation modes ispresented below.

A first operation mode is begun at a known point in time in the timingsequence of a received TDMA signal in an empty time slot following asignal slot and preceding another signal slot in which the signal to bedetected is to be provided. In the first mode, AGC loop 200 is opened,hence the feedback loop is not operational. At this stage, switch 244 isopen and switches 236 and 238 are closed. Voltage source V_(PRESET) 234charges integrating capacitor C_(AGC) 232. The voltage value isdetermined so that the attenuation of AGC amplifier 210 will be minimal.Typically, the attenuation value is substantially zero. The timerequired for charging integrating capacitor C_(AGC) 232 is determined bya time constant related to the product of the resistance value ofdamping resistor R_(AGC) 230 value and the capacitance value ofintegrating capacitor C_(AGC) 232. The first operation mode isterminated when the charging of integrating capacitor C_(AGC) 232 iscompleted.

At the beginning of the second operation mode, controller 226 opensswitch 236, thereby disconnecting voltage source V_(PRESET) 234 fromintegrating capacitor C_(AGC) 232. The remainder of the charge atintegrating capacitor C_(AGC) 232 defines the value of control signal240 and hence, the gain (or attenuation) of AGC amplifier 210.Controller 226 further closes switch 244, thereby closing AGC feedbackloop 200. AGC detector 218 determines the input signal level appliedthereto, based on determining the vector sum of the I and Q components(obtained from the sum of squares of the I and Q components), andprovides the output signal to integrating capacitor C_(AGC) 232. Thevoltage at integrating capacitor C_(AGC) 232 determines the gain of AGCamplifier 210. The beginning of the second operation mode falls in anempty time slot before the next signal slot, AGC detector 218 willtherefore first detect ambient noise of the system. Upon detection ofthis noise, AGC detector 218 provides an output signal which is appliedto adjust the gain of AGC amplifier 210, thereby increasing ordecreasing (or not changing) the attenuation of the noise as describedabove.

The shape of the gain response of AGC detector 218 and hence, the gainof AGC loop 200 depends in a non-linear manner on the input signal levelat the AGC detector 218. This gain is higher for signals that aregreater than a desired signal value (AGC threshold) and low for signalsthat are below the threshold. An exemplary relationship for the gainvariation can have the following form:G=G ₀ +kS ^(1+Δ),  (Equation 1)where G is the gain of AGC loop 200, S is the signal level and G₀, k and▭ are predetermined parameters (G₀, k,

. It is noted, that

can be a function of S.

The bandwidth of AGC loop 200 also depends on the signal level. Since inthe type of signal to be detected, the slot, which precedes a signalslot, is generally empty, AGC loop 200 must be able to adapt itself tovery fast changing signal levels. The signal rise time can be less than0.2 ms and the range of the signal can exceed 80 dB. This requires theloop bandwidth to be maximal for high level signals, so that the AGCattack (settling) time of the loop 200 is less than 0.2 ms. The attackperiod of AGC loop 200 is the minimum time period which is required forthe AGC loop to reach steady state operation in response to a change ininput power level when a signal is first detected. Typically, thedependence of the loop bandwidth on the signal level can be proportionalto the derivative of the loop gain with respect to the signal level, andis of a form:BW=A·k·(1+Δ)·S ^(Δ),  (Equation 2)where BW is a loop bandwidth, and A is a predetermined parameter.

The attack period of AGC loop 200 depends on the value of integratingcapacitor C_(AGC) 232. To minimize the attack period, the value ofintegrating capacitor C_(AGC) 232 must be as small as possible,consistent with maintaining a stable loop. A practical limit for thevalue of integrating capacitor C_(AGC) 232 is set by the loop dynamics.If the value of integrating capacitor C_(AGC) 232 is too small, thenthere is a significant overshoot in the loop response, which leads tosignal distortions at the beginning of the signal receive slot. Thisproblem is solved by including the connection of damping resistorR_(AGC) 230 in series with integrating capacitor C_(AGC) 232. Thisconnection enables the stability of the AGC loop to be improved andenables its response time to be reduced.

Reference is now made to FIG. 2, which is a graphical illustration ofthe dependence of the gain of AGC loop 200 on the signal level in aknown manner.

Typically, the dependence of the gain of AGC loop 200 gain on the signallevel is governed by Equation 1. For signal levels that are below adesired signal level (AGC threshold), the gain variations of AGC loop200 are comparatively small. When the signal level exceeds an AGCthreshold, the gain of AGC loop 200 begins to increase rapidly. Theslope of the curve, which is proportional to the bandwidth of AGC loop200, is steep for large signals above the threshold and not steep forsmall signals below the threshold. It means that AGC loop 200 has a fastresponse for signals which exceed the threshold signal level and a slowresponse for low-level signals.

The second operation mode continues until the end of the signal slot.

Reference is further made to FIG. 3, which is a schematic illustrationof a method for operating AGC loop 200 (FIG. 1).

In step 250, AGC loop 200 is opened. With reference to FIG. 1,controller 226 opens switch 244, thereby disconnecting AGC detector 218from switch 238 and driver 216.

In step 252, a minimal attenuation of AGC amplifier 210 is set. Withreference to FIG. 1, controller 226 closes switches 236 and 238. Voltagesource V_(PRESET) 234 charges integrating capacitor C_(AGC) 232. Thetime required for charging integrating capacitor C_(AGC) 232 isdetermined by the product of the values of the resistance value ofdamping resistor R_(AGC) and the capacitance value of integratingcapacitor C_(AGC) 232. Controller 226 opens switch 236 when the chargingof integrating capacitor C_(AGC) 232 is completed. The voltage fromcharged integrating capacitor C_(AGC) 232 is provided to AGC amplifier210 via damping resistor R_(AGC) 230, switch 238 and driver 216. Thevoltage value is determined so that the attenuation of AGC amplifier 210will be minimal.

In step 254, AGC feedback loop is closed. With reference to FIG. 1,controller 226 closes switch 244, thereby closing the AGC feedback loop.AGC detector 218 receives a baseband signal, produces an output signaland provides it to integrating capacitor C_(AGC) 232 via switches 244and 238. Since this operation is performed at times preceding the signalslots, AGC detector 218 will typically detect ambient noise of thesystem.

In step 256, a fast AGC attack takes place. With reference to FIG. 1,the circuit works with the feedback loop of AGC loop 200 closed. AGCdetector 218 determines a level of the sum of squares of the I and Qcomponents of the input signal, and provides its output signal tointegrating capacitor C_(AGC) 232, via switches 244, 238 and dampingresistor R_(AGC) 230. The voltage at integrating capacitor C_(AGC) 232determines the gain of AGC amplifier 210. At the beginning of the signalslot, AGC detector 218 will detect a fast increase of a signal level(giving the fast AGC attack). With reference to FIG. 2, both the gainand the bandwidth of AGC detector 218 are maximal for large, rapidlyvarying signals. Consequently, the response time of the AGC feedbackloop is minimal. As the signal approaches the desired threshold, thegain of AGC detector 218 decreases. This enables the system to proceedto the steady state operation mode with a minimal overshooting. Thesettling procedure is helped by the use of the variable gain amplifier215 in accordance with the invention in the manner to be described laterwith reference to FIGS. 5 and 6.

In step 258 shown in FIG. 3, the system proceeds to the steady stateoperation mode. With reference to FIG. 1, after detecting the fast AGCattack, AGC detector 218 rapidly reduces the gain of AGC loop 200. As aresult, the output baseband signal level approaches the desired value.AGC detector 218 continues to monitor and adjust the signal level withina comparatively narrow value range, close to the AGC threshold. Thissteady state operation mode continues until the end of the signal slot.

Reference is now made to FIG. 4, which is a schematic illustration ofdifferent operation modes of AGC loop 200. A first operation mode (OM1)corresponds to steps 250 and 252 of FIG. 3. At these steps, the AGCfeedback loop is closed and the attenuation of AGC amplifier 210 is setto a minimal level. A second operation mode (OM2) corresponds to steps254, 256 and 258 of FIG. 3. In this mode, AGC detector 218 of FIG. 1monitors the signal level and controls the loop gain accordingly. At thebeginning of the signal slot there is a short period of the fast AGCattack, accompanied by an overshoot. The duration of the fast AGC attackis typically less than 0.2 ms. The circuit rapidly recovers from theovershoot and continues to operate in the steady state mode until theend of the signal slot.

The role played by the variable gain amplifier 215 (FIG. 1) in the fastattack of the AGC circuit 200 will now be described. Reference is firstmade to FIG. 5. In FIG. 5, two curves are shown, namely a curve Acorresponding to a high gain of the variable gain amplifier 215 of thecircuit 200 and a curve B corresponding to a lower gain of the amplifier215. For each of the curves A and B the voltage at the output of thevariable gain amplifier 215 (signal 220 in FIG. 1) is shown as afunction of time. When an AGC attack occurs at a time T0 the voltage atthe receiver output (output of the variable gain amplifier 215) risessteeply until a peak is reached at a time TP after which the voltagegradually falls until it becomes settled at a time TS. For curve A thevoltage reaches a significantly higher peak than that reached by curveB. The higher value of the peak of curve A contributes to an undesirablygreater overshoot as described earlier. The gain of the feedback loop ofthe circuit 200 may be adjusted by varying the gain of the variable gainamplifier 215. Thus, the response of the feedback loop may be selectedby control of the variable gain amplifier to follow either curve A orcurve B. For example, when the amplifier 215 has nominal gain, the curveA may be followed and when the amplifier 215 has a reduced gain of 12 dBless than nominal the curve B may be followed.

Reference is now made to FIG. 6. The curves A and B shown in FIG. 5 areshown again in FIG. 6 but in this case a further curve C is shown. CurveC represents the voltage observed in practice as an output of thevariable gain amplifier 215 by applying appropriate control signalsthereto from the controller 226. After a fast attack begins at a timeT0, the gain of the feedback loop of the circuit 200 has a reduced levelby selecting a reduced gain of the amplifier 215 until a time T1. Duringthis period the voltage comprising the receiver output signal (amplifier215 output) or curve C follows lower curve B. At time T1 the gain of theamplifier 215 is increased. This causes the receiver output signal torise above curve B but because some operation of the feedback loop AGCcontrol of the AGC amplifier 210 has already occurred between T0 and T1the rise following T1 is relatively small compared with the differencebetween the peaks of the two curves A and B. Thus, the curve C quicklyreaches a plateau and settles to a substantially constant level at atime T2. The time T2 is much less than the time TS required for settlingof curve A or curve B alone.

Thus, the gain of amplifier 215 is increased at the time T1 to cause thereceiver output signal to follow curve C. The gain of amplifier 215 ischanged by application of control input signals from the controller 226(FIG. 1). The change of gain of 12 dB for the variable gain amplifier215 was chosen because it corresponds to the change giving an overshootof OS in the output voltage of the variable gain amplifier 215 shown inFIG. 6, namely the difference in voltage between the peak voltage andsteady state voltage obtained after time TS for curve A.

Reference is now made to FIG. 7, which is a schematic illustration of afast attack AGC loop, generally referenced 400, constructed and operablein accordance with a further embodiment of the present invention.

An AGC loop 400 includes an AGC amplifier 410, a down mixer 412, adriver 416, a low-pass filter 414, avariable gain amplifier 415, anon-channel detector 418, an off-channel detector 420, a controller 426,a damping resistor R_(AGC) 430, an integrating capacitor C_(AGC) 432, avoltage source V_(PRESET) 434 and four switches 436, 438, 442 and 444.AGC amplifier 410 is coupled to down mixer 412 and to driver 416.Low-pass filter 414 is coupled to down mixer 412 and to variable gainamplifier 415. Low pass filter 415 is connected to on-channel detector418. On-channel detector 418 is coupled to switch 444. Off-channeldetector 420 is coupled to down mixer 412 and to switch 442. Controller426 is coupled to switches 436, 438, 442 and 444. Driver 416 is coupledto switches 438, 442 and 444. Voltage source V_(PRESET) 434 is coupledto switch 436. Damping resistor R_(AGC) 430 is coupled to integratingcapacitor C_(AGC) 432 and to switch 438.

AGC loop 400 includes a forward transmission path 411 and two feedbackloops 421 and 423, coupled across the forward path 411. The forwardtransmission path 411 includes AGC amplifier 410, down mixer 412,low-pass filter 414 and variable gain amplifier 415. The input for AGCloop 400 is an RF input signal applied along the forward transmissionpath 411 at amplifier 410, and the output of the AGC loop 400 is abaseband signal having I and Q components delivered from the forwardtransmission path 411 at amplifier 415. The feedback loop 423 includesoff-channel detector 420, which is coupled between the down mixer 412output and low-pass filter 414 input. Off-channel detector 420 detectssignals which are filtered out by the low pass filter 414 as well asthose which are passed by the filter 414. Off-channel detector 420controls the amplitude of adjacent channel (undesired) signals in theforward path. The feedback loop 421 includes on-channel detector 418,which is coupled to the output of low-pass filter 414. On-channeldetector 418 controls the amplitude of on-channel (desired) signals inthe forward path 411. Off-channel detector 420 and on-channel detector418 provide their respective output signals to integrating capacitorC_(AGC) 432. Driver 416 controls the gain of AGC amplifier 410 byproviding a control signal 450. An exemplary dependence of theattenuation of AGC amplifier 410 on the voltage on integrating capacitorC_(AGC) 432, can be a linear dependence of the decibels of attenuationon voltage. It is noted that there can be other types of dependencies ofthe attenuation of AGC amplifier 410 on the voltage on integratingcapacitor C_(AGC) 432. The value of control signal 450 depends on theoperation mode of AGC loop 400. Detailed description of each of theoperation modes is presented below.

At the beginning of the first operation mode, which corresponds to timeinstances preceding the signal slot, AGC loop 400 is open. Consequently,the feedback loops are not operating. Controller 426 opens switches 442and 444 and closes switches 436 and 438. Voltage source V_(PRESET) 434charges integrating capacitor C_(AGC) 432. The voltage value isdetermined so that the attenuation of AGC amplifier 410 will be minimal.The time period which is required for charging integrating capacitorC_(AGC) 432 is specified by a product of the resistance value of dampingresistor R_(AGC) 430 and the capacitance value of integrating capacitorC_(AGC) 432. The first operation mode is terminated when the charging ofintegrating capacitor C_(AGC) 432 is completed.

At the beginning of the second operation mode, controller 426 opensswitch 436, thereby disconnecting voltage source V_(PRESET) 434 fromintegrating capacitor C_(AGC) 432. The remainder of the charge atintegrating capacitor C_(AGC) 432 defines the value of control signal450 and, hence, the gain (or attenuation) of AGC amplifier 410.Controller 426 further closes switches 444 and 442, thereby closing theAGC feedback loops. On-channel detector 418 monitors the desiredbaseband signal, and provides its output signal to the integratingcapacitor C_(AGC) 432. Off-channel detector 420 monitors undesiredsignal on adjacent channels. The gain of this detector is determined sothat it reacts only to strong signals, which are mainly off-channelsignals which are outside of the pass band of low-pass filter 414. Thisis because on-channel signals will already have been detected as signalsabove a lower threshold at the on-channel detector 418. Off-channeldetector 420 provides an output signal which is combined with that ofthe on-channel detector 418 and fed to integrating capacitor C_(AGC)432, via switches 442 and 438 and damping resistor R_(AGC) 430.

Both detectors 418 and 420 determine a level of signal overshoot of theinput signals applied to those detectors. The shape of the responsecurve of detectors 418 and 420 depends in a non-linear manner on thesignal level and can be described by Equation 1 given earlier. Thegraphical illustration of this dependence is as presented in FIG. 2. Thebandwidth of AGC loop 400 also depends on the signal level. Since in thetype of signal to be detected the slot, which precedes a signal slot, isgenerally empty, AGC loop 400 must be able to adapt itself rapidly tovery fast changing signal levels at the beginning of the signal slot.The signal rise time period can be less than 0.2 ms and the dynamicrange of the signal can exceed 80 dB. This requires the loop bandwidthto be maximal for high level signals, so that the AGC attack (settling)period is less than 0.2 ms. Typically, the dependence of the loopbandwidth on the signal level can be proportional to the derivative ofthe loop gain with respect to the signal level, and is described byEquation 2. Since the beginning of the second operation mode falls in anempty time slot which precedes the signal slot, off-channel detector 420and on-channel detector 418 will first detect an ambient noise of thesystem. Upon detection of this noise, both detectors provide arespective output signal to AGC amplifier 410, thereby increasing theattenuation of the signal. In the second operation mode, both detectorsdetect the beginning of the signal slot, which is accompanied by a sharpincrease in the signal level. According to Equations 1 and 2 and FIG. 2,both the gain and the bandwidth of on-channel detector 418 andoff-channel detector 420 are maximal for large, rapidly varying signals.Consequently, the response time of the AGC feedback loops is minimal. Asthe signal approaches the desired threshold, the gain of on-channeldetector 418 decreases. This reduces overshooting of the system whilstit proceeds to steady state operation. The second operation mode iscompleted at the end of the signal slot. It is noted that the methodillustrated in FIG. 3 can be used for operating AGC loop 400.

In order to reduce further the overshoot of the system comprising theloop 400 shown in FIG. 7, the gain of the variable gain amplifier 415 isvaried by controller 426 in the same manner as amplifier 215 in FIG. 1.Thus, the gain of the combined feedback loop arrangement shown in FIG. 7is set to give a function represented by curve C in FIG. 6 by the gainlevel of amplifier 415 being set to a reduced level by controller 426during a period from T0 to T1 as illustrated in FIG. 6 and being set toa higher level, e.g. 12 dB higher, during a period from T1 to T2 andonward until the end of the input R.F. signal. The gain change at timeT1 was chosen in practice to be 12 dB because the overshoot labelled OSin FIG. 6 of curve A over required curve C was found to be 12 dB.

In a further embodiment of the invention (not shown), thefilter-amplifier pair which includes the further variable gainamplifier, namely the low pass filter 414 and the amplifier 415 in thecircuit of FIG. 7, may be replaced by a plurality, e.g. a chain, offilter-amplifier pairs. One of the amplifiers, e.g. the last of suchamplifiers in the forward transmission path, may be a variable gainamplifier operated in the same manner as the amplifier 215 of FIG. 1 andthe amplifier 415 in FIG. 7.

1. An automatic gain control (AGC) circuit comprising: a forwardtransmission path having, in use, applied at its input an input RFsignal and to provide at its output an output signal; a variable gainAGC amplifier in the forward transmission path for processing the inputRF signal, which amplifier has a control input and is responsive to acontrol signal applied at its control input to vary its gain; a feedbackloop coupled from the output of said forward transmission path and tosaid control input of said AGC amplifier, said feedback loop including asignal detector that has a predetermined non-linear gain response,depending on an input signal level, the gain being higher for greaterinput signal strength; an integrator coupled to said control input ofsaid amplifier; a voltage source coupled to said integrator and to saidcontrol input of said amplifier; and a further variable gain device forvarying the gain or attenuation of a signal applied as an input signalto the control input of said AGC amplifier.
 2. A circuit according toclaim 1 wherein the further variable gain device comprises a furthervariable gain amplifier having a control input by which a control inputsignal may be applied in operation to vary the gain of the furthervariable gain device.
 3. A circuit according to claim 1 wherein thefurther variable gain device is arranged to be operable to vary the gainof a signal applied as an input to said detector.
 4. A circuit accordingto claim 1 wherein the further variable gain device is included in theforward transmission path after the variable gain AGC amplifier.
 5. Acircuit according to claim 1 wherein the further variable gain devicehas a control input connected to a circuit control device providing inoperation input control signals to the further variable gain device toadjust the gain thereof.
 6. A circuit according to claim 1 wherein thefurther variable gain device is operable such that the signal applied asan input signal to the control input of the AGC amplifier via thefeedback loop is adjusted in gain during an attack and settling periodof the AGC circuit
 7. A circuit according to claim 6 wherein the furthervariable gain device is operable to have two or more gain levels duringan attack and settling period.
 8. A circuit according to claim 7 whereinthe gain of the further variable gain device is in operation adjusted sothat in a first part of the attack and settling period from a time T0when an input RF signal is first applied to the AGC amplifier until atime T1 the gain of the further variable gain device is set at a lowerlevel than in a second part the attack and settling period after thetime T1.
 9. A circuit according to claim 8 wherein the further variablegain device is operable such that during the said first part of theattack and settling period its gain is between 5 dB and 20 dB lower thanin the said second part of the attack period.
 10. A circuit according toclaim 8 wherein the time T1 is a time of at least 50 μsec after the timeT0 and the higher gain second part of the attack period starts at thetime T1.
 11. A circuit according to claim 10 wherein the time T1 is atime of between 100 μsec and 300 μsec after the time T0 and the highergain second part of the attack period starts.
 12. A circuit according toclaim 11 wherein the time T1 is a time of between 100 μsec and 200 μsecafter the time T0 and the higher gain second part of the attack periodstarts.
 13. A circuit according to claim 7 wherein in operation thedifference in gain between the two gain levels of the variable gaindevice corresponds substantially to the difference obtained for theoutput signal of the forward transmission path between a peak overshootlevel of the output signal of the forward transmission path obtainedusing the higher gain level and a steady state level of the signal to bereached after the attack and settling period.
 14. A circuit according toclaim 1 wherein the forward transmission path includes a down mixer towhich an output signal from the AGC amplifier is in operation applied toprovide a baseband output signal and the further variable gain device isarranged so that in operation it adjusts the gain of the baseband outputsignal provided as an output signal from the down mixer.
 15. An AGCcircuit according to claim 14 wherein the baseband output signal of themixer includes as phase components an in-phase (I) component and aquadrature (Q) component.
 16. An AGC circuit according to claim 15wherein the signal detector comprises a sum of squares (SOS) detectorproviding an output related to the sum of the squares of the level ofthe I and Q phase components.
 17. A circuit according to claim 14wherein the circuit includes one or more filters located in the forwardtransmission path after the AGC amplifier and after the mixer andwherein the variable gain device is located in the forward transmissionpath after the or one of the filters.
 18. A circuit according to claim17 wherein the forward transmission path includes a plurality offilter-amplifier pairs and the further variable gain device comprisesone of the amplifiers of the filter-amplifier pairs.
 19. A circuitaccording to claim 18 wherein the variable gain device comprises thelast amplifier in plurality of filter-amplifier pairs.
 20. An AGCcircuit according to claim 1 wherein the forward transmission pathincludes a low pass filter and the variable gain device is connected tothe output of the low pass filter and the AGC circuit includes at leasttwo feedback loops connected between the forward transmission path andthe control input of the AGC amplifier, including a first feedback loopconnected to the forward transmission path before the low pass filterand a second feedback loop connected to the forward transmission pathafter the variable gain device, each of the feedback loops incorporatinga signal detector having a non-linear gain response.
 21. An AGC circuitaccording to claim 20 wherein the signal detector of the first feedbackloop has a signal strength detection threshold which is greater than thesignal strength detection threshold of the detector of the the secondfeedback loop.
 22. An AGC circuit according to claim 21 wherein aresponse of said signal detector to changes in the level of the signalpresented thereto is to provide an output signal of variable bandwidth,wherein the variable bandwidth is higher according to the strength ofthe input signal being higher.
 23. An AGC circuit according to claim 1wherein said integrator comprises an integrating capacitor and aresistor, the integrating capacitor having an output through theresistor coupled to said control input of said AGC amplifier, andwherein said circuit further comprises a voltage source which providesto said integrator, thereby determining a level of said control signal,a predetermined voltage for a predetermined preset time period beginningat a predetermined time.
 24. An AGC circuit according to claim 1 whereinthe control input to the AGC amplifier includes a driver providing inoperation a substantially linear change in gain or attenuation of theAGC amplifier in response to a change in the voltage applied thereto.25. An AGC circuit according to claim 1 which further includes switchingmeans operable to allow the AGC circuit to be switched between a firstmode of operation in which the or each feedback loop is not operationaland a second mode of operation in which the or each feedback loop isoperational, such modes being obtained at predetermined times forpredetermined time periods.
 26. An AGC circuit according to claim 25wherein the switching means includes an electrically operated switch forconnecting an output terminal of the signal detector to the integrator,one or more electrically controlled switches for connecting a voltagesource to the integrator and the integrator to the control input of thevariable gain amplifier and a controller for providing signals tooperate the switches to provide switching between the first and secondmodes.
 27. An RF receiver including an automatic gain control AGCcircuit comprising: a forward transmission path having, in use, appliedat its input an input RF signal and to provide at its output an outputsignal; a variable gain AGC amplifier in the forward transmission pathfor processing the input RF signal, which amplifier has a control inputand is responsive to a control signal applied at its control input to tovary its gain; a feedback loop, coupled from the output of said forwardtransmission path and to said control input of said AGC amplifier, saidfeedback loop including a signal detector that has a predeterminednon-linear gain response, depending on an input signal level, the gainbeing higher for treater input signal strength, an integrator, coupledto said control input of said amplifier; and, a voltage source, coupledto said integrator and to said control input of said amplifier, and afurther variable gain device for varying the gain or attenuation of asignal applied as an input signal to the control input of said AGCamplifier.
 28. An RF receiver according to claim 27 which is operable toreceive RF signals provided in a plurality of signal time slots, eachpair of adjacent signal time slots being interleaved by at least oneempty time slot.
 29. An RF receiver according to claim 28 wherein theAGC circuit has a first mode of operation in which the or each feedbackloop is not operational and a second mode of operation in which the oreach feedback loop is operational, such modes being obtained alternatelyat predetermined times for predetermined time intervals corresponding toa pattern of the signal time slots and empty time slots.
 30. An RFreceiver according to claim 29 wherein the first mode of operation isinitiated after the end of each signal time slot.
 31. An RF receiveraccording to claim 29 wherein the second mode of operation is initiatedbefore the start of each signal time slot.
 32. An RF receiver accordingto claim 27 wherein the receiver is operable in a direct mode ofoperation and the signal to be detected is a direct mode communicationssignal.
 33. An RF receiver according to claim 27 wherein the signal tobe detected is communicated in accordance with TETRA standards.